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| 19-2224; Rev 2; 9/02 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers General Description The MAX1901/MAX1902/MAX1904 are buck-topology, step-down, switch-mode, power-supply controllers that generate logic-supply voltages in battery-powered systems. These high-performance, dual/triple-output devices include on-board power-up sequencing, power-good signaling with delay, digital soft-start, secondary winding control, low dropout circuitry, internal frequency-compensation networks, and automatic bootstrapping. Up to 97% efficiency is achieved through synchronous rectification and Maxim's proprietary Idle ModeTM control scheme. Efficiency is greater than 80% over a 1000:1 load-current range, which extends battery life in system suspend or standby mode. Excellent dynamic response corrects output load transients within five clock cycles. Strong 1A on-board gate drivers ensure fast external Nchannel MOSFET switching. These devices feature a logic-controlled and synchronizable, fixed-frequency, pulse-width modulation (PWM) operating mode. This reduces noise and RF interference in sensitive mobile communications and pen-entry applications. Asserting the SKIP pin enables fixed-frequency mode, for lowest noise under all load conditions. The MAX1901/MAX1902/MAX1904 include two PWM regulators, adjustable from 2.5V to 5.5V with fixed 5.0V and 3.3V modes. All these devices include secondary feedback regulation, and the MAX1902 contains a 12V/120mA linear regulator. The MAX1901/MAX1904 include a secondary feedback input (SECFB), plus a control pin (STEER) that selects which PWM (3.3V or 5V) receives the secondary feedback signal. SECFB provides a method for adjusting the secondary winding voltage regulation point with an external resistor divider, and is intended to aid in creating auxiliary voltages other than fixed 12V. The MAX1901/MAX1902 contain internal output overvoltage and undervoltage protection features. o o o o o o o o o o o o o o o o Features 97% Efficiency 4.2V to 30V Input Range 2.5V to 5.5V Dual Adjustable Outputs Selectable 3.3V and 5V Fixed or Adjustable Outputs (Dual ModeTM) 12V Linear Regulator Adjustable Secondary Feedback (MAX1901/MAX1904) 5V/50mA Linear Regulator Output Precision 2.5V Reference Output Programmable Power-Up Sequencing Power-Good (RESET) Output Output Overvoltage Protection (MAX1901/MAX1902) Output Undervoltage Shutdown (MAX1901/MAX1902) 333kHz/500kHz Low-Noise, Fixed-Frequency Operation Low-Dropout, 98% Duty-Factor Operation 2.5mW Typical Quiescent Power (12V input, both SMPSs on) 4A Typical Shutdown Current MAX1901/MAX1902/MAX1904 Ordering Information PART MAX1901EAI MAX1902EAI MAX1904EAI MAX1904ETJ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 SSOP 28 SSOP 28 SSOP 32 Thin QFN 5mm x 5mm Functional Diagram INPUT 5V (RTC) 5V LINEAR 12V LINEAR 12V ________________________Applications Notebook and Subnotebook Computers PDAs and Mobile Communicators Desktop CPU Local DC-DC Converters 3.3V 3.3V SMPS 5V SMPS 5V Idle Mode is a trademark of Maxim Integrated Products, Inc. Dual Mode is a trademark of Maxim Integrated Products, Inc. Pin Configurations appear at end of data sheet. ON/OFF POWER-UP SEQUENCE POWERGOOD RESET ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 ABSOLUTE MAXIMUM RATINGS V+ to GND ..............................................................-0.3V to +36V PGND to GND.....................................................................0.3V VL to GND ................................................................-0.3V to +6V BST3, BST5 to GND ..............................................-0.3V to +36V CSH3, CSH5 to GND................................................-0.3V to +6V FB3 to GND ..............................................-0.3V to (CSL3 + 0.3V) FB5 to GND ...............................................-0.3V to (CSL5 +0.3V) LX3 to BST3..............................................................-6V to +0.3V LX5 to BST5..............................................................-6V to +0.3V REF, SYNC, SEQ, STEER, SKIP, TIME/ON5, SECFB, RESET to GND ........-0.3V to (VL + 0.3V) VDD to GND. ...........................................................-0.3V to +20V RUN/ON3, SHDN to GND.............................-0.3V to (V+ + 0.3V) 12OUT to GND ..........................................-0.3V to (VDD + 0.3V) DL3, DL5 to PGND........................................-0.3V to (VL + 0.3V) DH3 to LX3 ..............................................-0.3V to (BST3 + 0.3V) DH5 to LX5 ..............................................-0.3V to (BST5 + 0.3V) VL, REF Short to GND ................................................Momentary 12OUT Short to GND..................................................Continuous REF Current...........................................................+5mA to -1mA VL Current.........................................................................+50mA 12OUT Current . .............................................................+200mA VDD Shunt Current. ...........................................................+15mA Continuous Power Dissipation (TA = +70C) 28-Pin SSOP (derate 9.52mW/C above +70C) ......762mW 32-Pin Thin QFN (derate 21.3mW/C above +70C) ..1702mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range ............................-65C to +160C Lead Temperature (soldering, 10s) ................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0, REF load = 0, SKIP = 0, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER MAIN SMPS CONTROLLERS Input Voltage Range 3V Output Voltage in Adjustable Mode 3V Output Voltage in Fixed Mode 5V Output Voltage in Adjustable Mode 5V Output Voltage in Fixed Mode Output Voltage Adjust Range Adjustable-Mode Threshold Voltage Load Regulation Line Regulation Current-Limit Threshold Idle Mode Threshold Soft-Start Ramp Time Oscillator Frequency V+ = 4.2V to 30V, CSH3 - CSL3 = 0, CSL3 tied to FB3 V+ = 4.2V to 30V, 0 < CSH3 - CSL3 < 80mV, FB3 = 0 V+ = 4.2V to 30V, CSH5 - CSL5 = 0, CSL5 tied to FB5 V+ = 5.3V to 30V, 0 < CSH5 - CSL5 < 80mV, FB5 = 0 Either SMPS Dual-mode comparator Either SMPS, 0 < CSH_ - CSL_ < 80mV Either SMPS, 5.2V < V+ < 30V CSH3 - CSL3 or CSH5 - CSL5 SKIP = VL or VDD < 13V or SECFB < 2.44V SKIP = 0, not tested From enable to 95% full current limit with respect to fOSC (Note 1) SYNC = VL SYNC = 0 450 283 80 -50 10 4.2 2.42 3.20 2.42 4.85 REF 0.5 -2 0.03 100 -100 25 512 500 333 550 383 120 -150 40 2.5 3.39 2.5 5.13 30.0 2.58 3.47 2.58 5.25 5.5 1.1 V V V V V V V % %/V mV mV clks kHz CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0, REF load = 0, SKIP = 0, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Maximum Duty Factor SYNC Input High-Pulse Width SYNC Input Low-Pulse Width SYNC Rise/Fall Time SYNC Input Frequency Range Current-Sense Input Leakage Current FLYBACK CONTROLLER VDD Regulation Threshold SECFB Regulation Threshold DL Pulse Width VDD Shunt Threshold VDD Shunt Sink Current VDD Leakage Current 12V LINEAR REGULATOR (Note 3) 12OUT Output Voltage 12OUT Current Limit Quiescent VDD Current INTERNAL REGULATOR AND REFERENCE VL Output Voltage VL Undervoltage Lockout-Fault Threshold VL Switchover Threshold REF Output Voltage REF Load Regulation REF Sink Current REF Fault-Lockout Voltage V+ Operating Supply Current V+ Standby Supply Current V+ Standby Supply Current in Dropout V+ Shutdown Supply Current Falling edge VL switched over to CSL5, 5V SMPS on V+ = 5.5V to 30V, both SMPSs off, includes current into SHDN V+ = 4.2V to 5.5V, both SMPSs off, includes current into SHDN V+ = 4.0V to 30V, SHDN = 0 Both SMPSs enabled, FB3 = FB5 = 0, CSL3 = CSH3 = 3.5V, CSL5 = CSH5 = 5.3V (Note 3) MAX1901/MAX1904 SHDN = V+, RUN/ON3 = TIME/ON5 = 0, 5.4V < V+ < 30V, 0mA < ILOAD < 50mA Falling edge, hysteresis = 1% Rising edge of CSL5, hysteresis = 1% No external load (Note 5) 0 < ILOAD < 50A 0 < ILOAD < 5mA 10 1.8 5 30 50 4 2.5 1.5 2.4 50 60 200 10 4 mW 4 4.7 3.5 4.2 2.45 3.6 4.5 2.5 5.1 3.7 4.7 2.55 12.5 100.0 V V V V mV A V A A A A 13V < VDD < 18V, 0 < ILOAD < 120mA 12OUT forced to 11V, VDD = 13V VDD = 18V, run mode, no 12OUT load 11.65 12.10 150 50 100 12.50 V mA A Falling edge (Note 3) Falling edge (MAX1901/MAX1904) VDD < 13V or SECFB < 2.44V Rising edge, hysteresis = 1% (Note 3) VDD = 20V (Note 3) VDD = 5V, off mode (Notes 3, 4) 18 10 30 13 2.44 0.75 20 14 2.60 V V s V mA A V+ = VL = 0, CSL3 = CSH3 = CSL5 = CSH5 = 5.5V SYNC = VL SYNC = 0 (Note 2) Not tested Not tested Not tested 400 0.01 CONDITIONS MIN 95 96.5 200 200 200 583 10 TYP 97 98 MAX UNITS % ns ns ns kHz A MAX1901/MAX1902/MAX1904 Quiescent Power Consumption _______________________________________________________________________________________ 3 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0, REF load = 0, SKIP = 0, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER FAULT DETECTION (MAX1901/MAX1902) Overvoltage Trip Threshold Overvoltage Fault Propagation Delay Output Undervoltage Threshold Output Undervoltage Lockout Time Thermal-Shutdown Threshold RESET RESET Trip Threshold RESET Propagation Delay RESET Delay Time INPUTS AND OUTPUTS Feedback-Input Leakage Current Logic Input-Low Voltage Logic Input-High Voltage Input Leakage Current Logic Output-Low Voltage Logic Output-High Current TIME/ON5 Input Trip Level TIME/ON5 Source Current TIME/ON5 On-Resistance Gate-Driver Sink/Source Current Gate-Driver On-Resistance FB3, FB5; SECFB = 2.6V RUN/ON3, SKIP, TIME/ON5 (SEQ = REF), SHDN, STEER, SYNC RUN/ON3, SKIP, TIME/ON5 (SEQ = REF), SHDN, STEER, SYNC RUN/ON3, SKIP, TIME/ON5 (SEQ = REF), SHDN, STEER, SYNC, SEQ; VPIN = 0V or 3.3V RESET, ISINK = 4mA RESET = 3.5V SEQ = 0 or VL TIME/ON5 = 0, SEQ = 0 or VL TIME/ON5; RUN/ON3 = 0, SEQ = 0 or VL DL3, DH3, DL5, DH5; forced to 2V High or low (Note 6) SSOP package QFN package 1 2.4 2.5 3 15 1 1.5 1.5 7 8 2.6 3.5 80 2.4 1 0.4 1 50 0.6 nA V V A V mA V A A With respect to unloaded output voltage, falling edge; typical hysteresis = 1% Falling edge, CSL_ driven 2% below RESET trip threshold With respect to fOSC 27,000 -7 -5.5 1.5 32,000 37,000 -4 % s clks With respect to unloaded output voltage CSL_ driven 2% above overvoltage trip threshold With respect to unloaded output voltage From each SMPS enabled, with respect to fOSC Typical hysteresis = 10C 60 5,000 4 7 1.5 70 6,144 150 80 7,000 10 % s % clks C CONDITIONS MIN TYP MAX UNITS 4 _______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 ELECTRICAL CHARACTERISTICS (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0, REF load = 0, SKIP = 0, TA = -40C to +85C, unless otherwise noted.) (Note 7) PARAMETER MAIN SMPS CONTROLLERS Input Voltage Range 3V Output Voltage in Adjustable Mode 3V Output Voltage in Fixed Mode 5V Output Voltage in Adjustable Mode 5V Output Voltage in Fixed Mode Output Voltage Adjust Range Adjustable-Mode Threshold Voltage Current-Limit Threshold Oscillator Frequency Maximum Duty Factor SYNC Input Frequency Range FLYBACK CONTROLLER VDD Regulation Threshold SECFB Regulation Threshold VDD Shunt Threshold VDD Shunt Sink Current 12V LINEAR REGULATOR (Note 3) 12OUT Output Voltage Quiescent VDD Current INTERNAL REGULATOR AND REFERENCE VL Output Voltage VL Undervoltage Lockout-Fault Threshold VL Switchover Threshold REF Output Voltage REF Load Regulation REF Sink Current REF Fault Lockout Voltage V+ Operating Supply Current Falling edge VL switched over to CSL5, 5V SMPS on SHDN = V+, RUN/ON3 = TIME/ON5 = 0, 5.4V < V+ < 30V, 0 < ILOAD < 50mA Falling edge, hysteresis = 1% Rising edge of CSL5, hysteresis = 1% No external load (Note 5) 0 < ILOAD < 50A 0 < ILOAD < 5mA 10 1.8 2.4 50 4.7 3.5 4.2 2.45 5.1 3.7 4.7 2.55 12.5 100.0 V V V V mV A V A 13V < VDD < 18V, 0mA < ILOAD < 100mA VDD = 18V, run mode, no 12OUT load 11.65 12.50 100 V A Falling edge (Note 3) Falling edge (MAX1901/MAX1904) Rising edge, hysteresis = 1% (Note 3) VDD = 20V (Note 3) 13 2.44 18 10 14 2.60 20 V V V mA V+ = 4.2V to 30V, CSH3 - CSL3 = 0, CSL3 tied to FB3 V+ = 4.2V to 30V, 0 < CSH3 - CSL3 < 80mV, FB3 = 0 V+ = 4.2V to 30V, CSH5 - CSL5 = 0, CSL5 tied to FB5 V+ = 5.3V to 30V, 0 < CSH5 - CSL5 < 80mV, FB5 = 0 Either SMPS Dual-mode comparator CSH3 - CSL3 or CSH5 - CSL5 SKIP = VL or VDD < 13V or SECFB < 2.44V SYNC = VL SYNC = 0 SYNC = VL SYNC = 0 (Note 2) 4.2 2.42 3.20 2.42 4.85 REF 0.5 80 -50 450 283 95 97 400 583 30.0 2.58 3.47 2.58 5.25 5.5 1.1 120 -150 550 383 V V V V V V V mV kHz % kHz CONDITIONS MIN TYP MAX UNITS _______________________________________________________________________________________ 5 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, both PWMs on, SYNC = VL, VL load = 0, REF load = 0, SKIP = 0, TA = -40C to +85C, unless otherwise noted.) (Note 7) PARAMETER V+ Standby Supply Current V+ Standby Supply Current in Dropout V+ Shutdown Supply Current CONDITIONS V+ = 5.5V to 30V, both SMPSs off, includes current into SHDN V+ = 4.2V to 5.5V, both SMPSs off, includes current into SHDN V+ = 4.0V to 30V, SHDN = 0 Both SMPSs enabled, FB3 = FB5 = 0, CSL3 = CSH3 = 3.5V, CSL5 = CSH5 = 5.3V (Note 3) MAX1901/MAX1904 MIN TYP MAX 60 200 10 4 mW 4 UNITS A A A Quiescent Power Consumption FAULT DETECTION (MAX1901/MAX1902) Overvoltage Trip Threshold Output Undervoltage Threshold Output Undervoltage Lockout Time RESET RESET Trip Threshold RESET Delay Time INPUTS AND OUTPUTS Feedback-Input Leakage Current Logic Input-Low Voltage Logic Input-High Voltage Logic Output-Low Voltage Logic Output-High Current TIME/ON5 Input Trip Level TIME/ON5 Source Current TIME/ON5 On-Resistance Gate-Driver On-Resistance FB3, FB5; SECFB = 2.6V RUN/ON3, SKIP, TIME/ON5 (SEQ = REF), SHDN, STEER, SYNC RUN/ON3, SKIP, TIME/ON5 (SEQ = REF), SHDN, STEER, SYNC RESET, ISINK = 4mA RESET = 3.5V SEQ = 0 or VL TIME/ON5 = 0, SEQ = 0 or VL TIME/ON5; RUN/ON3 = 0, SEQ = 0 or VL High or low (Note 6) 1 2.4 2.5 2.6 3.5 80 2.4 0.4 50 0.6 nA V V V mA V A With respect to unloaded output voltage, falling edge; typical hysteresis = 1% With respect to fOSC -7 27,000 -4 37,000 % clks With respect to unloaded output voltage With respect to unloaded output voltage From each SMPS enabled, with respect to fOSC 4 60 5,000 10 80 7,000 % % clks Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 6 SSOP package 7 QFN package 8 Each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mV increments. High duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating frequency (see the Dropout Operation section). MAX1902 only. Off mode for the 12V linear regulator occurs when the SMPS that has flyback feedback (VDD) steered to it is disabled. In situations where the main outputs are being held up by external keep-alive supplies, turning off the 12OUT regulator prevents a leakage path from the output-referred flyback winding, through the rectifier, and into VDD. Since the reference uses VL as its supply, the reference's V+ line-regulation error is insignificant. Production testing limitations due to package handing require relaxed maximum on-resistance specifications for the thin QFN package. The SSOP and thin QFN package contain the same die, and the thin QFN package imposes no additional resistance incircuit. Specifications from to 0C to -40C are guaranteed by design, not production tested. _______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Typical Operating Characteristics (Circuit of Figure 1, Table 1, 6A/500kHz components, TA = +25C, unless otherwise noted.) EFFICIENCY vs. 5V OUTPUT CURRENT MAX1901 toc01 EFFICIENCY vs. 3.3V OUTPUT CURRENT MAX1901 toc02 MAXIMUM VDD OUTPUT CURRENT vs. INPUT VOLTAGE MAXIMUM VDD OUTPUT CURRENT (mA) 5V LOAD = 3A 600 5V LOAD = 0 400 MAX1901 toc03 100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.001 0.01 0.1 ON5 = 5V ON3 = 0V f = 500kHz MAX1901/MAX1904 1 V+ = 15V V+ = 6V 100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 ON5 = ON3 = 5V f = 500kHz MAX1901/MAX1904 0.001 0.01 0.1 1 V+ = 15V V+ = 6V 800 200 0 10 0 5 10 INPUT VOLTAGE (V) 15 20 3.3V OUTPUT CURRENT (A) 10 5V OUTPUT CURRENT (A) NO LOAD INPUT CURRENT vs. INPUT VOLTAGE SKIP = VL MAX1901 toc04 V+ STANDBY INPUT CURRENT vs. INPUT VOLTAGE MAX1901 toc05 SHUTDOWN INPUT CURRENT vs. INPUT VOLTAGE SHDN = 0V 8 INPUT CURRENT (A) MAX1901 toc06 100 10,000 10 INPUT CURRENT (mA) INPUT CURRENT (A) 10 1000 6 1 SKIP = 0V 0.1 ON5 = ON3 = 5V NO LOAD 0.01 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 100 4 10 ON5 = ON3 = 0V NO LOAD 1 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 2 0 0 5 10 15 20 25 30 INPUT VOLTAGE (V) MINIMUM VIN TO VOUT DIFFERENTIAL vs. 5V OUTPUT CURRENT 1000 MINIMUM VIN TO VOUT DIFFERENTIAL (mV) MAX1901 toc07 SWITCHING FREQUENCY vs. LOAD CURRENT MAX1901 toc08 VL REGULATOR OUTPUT VOLTAGE vs. OUTPUT CURRENT VIN = 15V ON3 = ON5 = 0V MAX1901 toc09 1000 3.3V, VIN = 15V 100 5.00 SWITCHING FREQUENCY (kHz) f = 500kHz 100 f = 333kHz VL OUTPUT VOLTAGE (V) 10 4.98 5V, VIN = 15V 10 3.3V, VIN = 6.5V 5V, VIN = 6.5V 4.96 4.94 1 0.1 4.92 VOUT > 4.8V 10 0.001 4.90 0.001 0.01 0.1 LOAD CURRENT (A) 1 0 10 20 30 40 50 OUTPUT CURRENT (mA) 0.01 0.1 1 10 5V OUTPUT CURRENT (A) _______________________________________________________________________________________ 7 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Typical Operating Characteristics (continued) (Circuit of Figure 1, Table 1, 6A/500kHz components, TA = +25C, unless otherwise noted.) REF OUTPUT VOLTAGE vs. OUTPUT CURRENT VIN = 15V ON3 = ON5 = 0 REF OUTPUT VOLTAGE (V) 2.500 MAX1901 toc10 STARTUP WAVEFORMS MAX1901 toc11 2.505 RUN 5V/div 0 3.3V OUTPUT 2V/div 2.495 0 TIME 2V/div 2.490 0 0 5V OUTPUT 5V/div 2.485 0 1 2 3 4 5 6 OUTPUT CURRENT (mA) 2ms/div SEQ = VL, O.O1F CAPACITOR ON TIME 5V LOAD TRANSIENT RESPONSE MAX1901 toc12 3.3V LOAD TRANSIENT RESPONSE MAX1901 toc13 5V OUTPUT 5OmV/div AC-COUPLED 10V 0 5A 0 VLX5 10V/div ILX5 5A/div 10V 0 5A 0 3.3V OUTPUT 5OmV/div AC-COUPLED VLX3 10V/div ILX3 5A/div 20s/div VIN = 8V, IOUT = 1A TO 5A 20s/div VIN = 8V, IOUT = 1A TO 5A 8 _______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Pin Description PIN SSOP 1 2 QFN 29 30 NAME CSH3 CSL3 FUNCTION Current-Sense Input for the 3.3V SMPS. Current-limit level is 100mV referred to CSL3. Current-Sense Input. Also serves as the feedback input in fixed-output mode. Feedback Input for the 3.3V SMPS. Regulates at FB3 = REF (approx. 2.5V) in adjustable mode. FB3 is a dual-mode input that also selects the 3.3V fixed output voltage setting when connected to GND. Connect FB3 to a resistor-divider for adjustable-output mode. 12V/120mA Linear-Regulator Output. Input supply comes from VDD. Bypass 12OUT to GND with 1F (min). Logic-Control Input for Secondary Feedback. Selects the PWM that uses a transformer and secondary feedback signal (SECFB): STEER = GND: 3.3V SMPS uses transformer STEER = VL: 5V SMPS uses transformer Supply Voltage Input for the 12OUT Linear Regulator. Also connects to an internal resistor-divider for secondary winding feedback and to an 18V overvoltage shunt regulator clamp. Secondary Winding Feedback Input. Normally connected to a resistor-divider from an auxiliary output. SECFB regulates at VSECFB = 2.5V (see the Secondary Feedback Regulation Loop section). Connect to VL if not used. Oscillator Synchronization and Frequency Select. Connect to VL for 500kHz operation; connect to GND for 333kHz operation. Can be driven at 400kHz to 583kHz for external synchronization. Dual-Purpose Timing Capacitor Pin and ON/OFF Control Input. See the Power-Up Sequencing and ON/OFF Controls section. Low-Noise Analog Ground and Feedback Reference Point 2.5V Reference Voltage Output. Bypass to GND with 1F (min). Logic-control input that disables idle mode when high. Connect to GND for normal use. Active-Low Timed Reset Output. RESET swings GND to VL. Goes high after a fixed 32,000 clock-cycle delay following power-up. Feedback Input for the 5V SMPS. Regulates at FB5 = REF (approx. 2.5V) in adjustable mode. FB5 is a dual-mode input that also selects the 5V fixed output voltage setting when connected to GND. Connect FB5 to a resistor-divider for adjustable-output mode. Current-Sense Input for the 5V SMPS. Also serves as the feedback input in fixed-output mode, and as the bootstrap supply input when the voltage on CSL5/VL is > 4.5V. Current-Sense Input for the 5V SMPS. Current-limit level is 100mV referred to CSL5. MAX1901/MAX1902/MAX1904 3 31 FB3 12OUT (MAX1902) 4 1 STEER (MAX1901/ MAX1904) VDD (MAX1902) 5 2 SECFB (MAX1901/ MAX1904) 6 3 SYNC 7 8 9 10 11 4 5 7 8 9 TIME/ON5 GND REF SKIP RESET 12 10 FB5 13 14 11 12 CSL5 CSH5 _______________________________________________________________________________________ 9 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Pin Description (continued) PIN QSOP QFN NAME FUNCTION Pin-strap input that selects the SMPS power-up sequence: SEQ = GND: 5V before 3.3V, RESET output determined by both outputs SEQ = REF: Separate ON3/ON5 controls, RESET output determined by 3.3V output SEQ = VL: 3.3V before 5V, RESET output determined by both outputs Gate-Drive Output for the 5V, High-Side N-Channel Switch. DH5 is a floating driver output that swings from LX5 to BST5, riding on the LX5 switching node voltage. Switching-Node (Inductor) Connection. Can swing 2V below ground without hazard. Boost Capacitor Connection for High-Side Gate Drive (0.1F) Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0 to VL. Power Ground 5V Internal Linear-Regulator Output. VL is also the supply-voltage rail for the chip. After the 5V SMPS output has reached 4.5V (typ), VL automatically switches to the output voltage through CSL5 for bootstrapping. Bypass to GND with 4.7F. VL supplies up to 25mA for external loads. Battery Voltage Input, 4.2V to 30V. Bypass V+ to PGND close to the IC with a 0.22F capacitor. Connects to a linear regulator that powers VL. Shutdown Control Input, Active Low. Logic threshold is set at approximately 1V. For automatic startup, connect SHDN to V+ through a 220k resistor and bypass SHDN to GND with a 0.01F capacitor. Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0 to VL. Boost Capacitor Connection for High-Side Gate Drive (0.1F) Switching-Node (Inductor) Connection. Can swing 2V below ground without hazard. Gate-Drive Output for the 3.3V, High-Side N-Channel Switch. DH3 is a floating driver output that swings from LX3 to BST3, riding on the LX3 switching-node voltage. ON/OFF Control Input. See the Power-Up Sequencing and ON/OFF Controls section. No Connection 15 13 SEQ 16 17 18 19 20 14 15 17 18 19 DH5 LX5 BST5 DL5 PGND 21 20 VL 22 21 V+ 23 24 25 26 27 28 -- 22 23 24 26 27 28 6, 16, 25, 32 SHDN DL3 BST3 LX3 DH3 RUN/ON3 N.C. 10 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 INPUT 7V TO 24V C3 10 0.1F V+ SHDN SECFB VL 4.7F Q1 C4 0.1F 5V OUTPUT R1 L1 Q2 0.1F LX5 DL5 MAX1901 LX3 SYNC BST5 DH5 BST3 DH3 0.1F Q3 C5 0.1F L2 R2 3.3V OUTPUT 0.1F ON/OFF 5V ALWAYS ON 4.7F C1 * MAX1904 DL3 GND PGND CSH3 CSL3 FB3 * Q4 C2 CSH5 CSL5 FB5 RESET 5V ON/OFF 3.3V ON/OFF TIME/ON5 SKIP RUN/ON3 STEER REF SEQ RESET OUTPUT 2.5V ALWAYS ON 1F *1A SCHOTTKY DIODE REQUIRED FOR THE MAX1901 (SEE THE OUTPUT OVERVOLTAGE PROTECTION SECTION). Figure 1. Standard 3.3V/5V Application Circuit (MAX1901/MAX1904) ______________________________________________________________________________________ 11 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Standard Application Circuit The basic MAX1901/MAX1904 dual-output 3.3V/5V buck converter (Figure 1) is easily adapted to meet a wide range of applications with inputs up to 28V by substituting components from Table 1. These circuits represent a good set of tradeoffs between cost, size, and efficiency, while staying within the worst-case specification limits for stress-related parameters, such as capacitor ripple current. Don't change the frequency of these circuits without first recalculating component values (particularly inductance value at maximum battery voltage). Adding a Schottky rectifier across each synchronous rectifier improves the efficiency of these circuits by approximately 1%, but this rectifier is otherwise not needed because the MOSFETs required for these circuits typically incorporate a high-speed silicon diode from drain to source. Use a Schottky rectifier rated at a DC current equal to at least one-third of the load current. Detailed Description The MAX1901/MAX1902/MAX1904 are dual, BiCMOS, switch-mode power-supply controllers designed primarily for buck-topology regulators in battery-powered applications where high-efficiency and low-quiescent supply current are critical. Light-load efficiency is enhanced by automatic Idle-Mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate-charge losses. Each step-down, power-switching circuit consists of two N-channel MOSFETs, a rectifier, and an LC output filter. The output voltage is the average AC voltage at the switching node, which is regulated by changing the duty cycle of the MOSFET switches. The gate-drive signal to the N-channel high-side MOSFET must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nF capacitor connected to BST_. Table 1. Component Selection for Standard 3.3V/5V Application COMPONENT Input Range Frequency Q1, Q3 High-Side MOSFETs Q2, Q4 Low-Side MOSFETs with Integrated Schottky Diodes C3 Input Capacitor C1 Output Capacitor C2 Output Capacitor R1, R2 Resistors L1 Inductor L2 Inductor 7V to 24V 333kHz 1/2 Fairchild FDS6982S or 1/2 International Rectifier IRF7901D1 1/2 Fairchild FDS6982S or 1/2 International Rectifier IRF7901D1 3 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM 150F, 6V POSCAP Sanyo 6TPC150M 2 150F, 4V POSCAP Sanyo 4TPC150M 0.018 Dale WSL2512-R018-F 10H, 4.5A Ferrite Sumida CDRH124-100 7.0H, 5.2A Ferrite Sumida CEI122-H-7R0 LOAD CURRENT 4A/333kHz 7V to 24V 500kHz 1/2 Fairchild FDS6982S or 1/2 International Rectifier IRF7901D1 1/2 Fairchild FDS6982S or 1/2 International Rectifier IRF7901D1 3 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM 150F, 6V POSCAP Sanyo 6TPC150M 2 150F, 4V POSCAP Sanyo 4TPC150M 0.018 Dale WSL2512-R018-F 7.0H, 5.2A Ferrite Sumida CEI122-H-7R0 5.6H, 5.2A Ferrite Sumida CEI122-H-5R6 4A/500kHz 7V to 24V 500kHz Fairchild FDS6612A or International Rectifier IRF7807V Fairchild FDS6670S or International Rectifier IRF7807DV1 4 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM 2 150F, 6V POSCAP Sanyo 6TPC150M 2 220F, 4V POSCAP Sanyo 4TPC220M 0.012 Dale WSL2512-R012-F 4.2H, 6.9A Ferrite Sumida CEI122-H-4R2 4.2H, 6.9A Ferrite Sumida CEI122-H-4R2 6A/500kHz 12 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Table 2. Component Suppliers MANUFACTURER Dale-Vishay Fairchild Semiconductor International Rectifier Sanyo Sumida Taiyo Yuden USA PHONE 402-564-3131 408-721-2181 310-322-3331 619-661-6835 847-956-0666 408-573-4150 FACTORY FAX 402-563-6418 408-721-1635 310-322-3332 619-661-1055 847-956-0702 408-573-4159 The MAX1901/MAX1902/MAX1904 contain ten major circuit blocks (Figure 2). The two pulse-width-modulation (PWM) controllers each consist of a Dual Mode feedback network and multiplexer, a multi-input PWM comparator, high-side and low-side gate drivers, and logic. MAX1901/ MAX1902 contain fault-protection circuits that monitor the main PWM outputs for undervoltage and overvoltage. A power-on sequence block controls the powerup timing of the main PWMs and determines whether one or both of the outputs are monitored for undervoltage faults. The MAX1902 includes a secondary feedback network and 12V linear regulator to generate a 12V output from a coupled-inductor flyback winding. The MAX1901/MAX1904 have a secondary feedback input (SECFB) instead, which allows a quasi-regulated, adjustable output, coupled-inductor flyback winding to be attached to either the 3.3V or the 5V main inductor. Bias generator blocks include the 5V IC internal rail (VL) linear regulator, 2.5V precision reference, and automatic bootstrap switchover circuit. The PWMs share a common 333kHz/500kHz synchronizable oscillator. These internal IC blocks aren't powered directly from the battery. Instead, the 5V VL linear regulator steps down the battery voltage to supply both VL and the gate drivers. The synchronous-switch gate drivers are directly powered from VL, while the high-side switch gate drivers are indirectly powered from V L via an external diode-capacitor boost circuit. An automatic bootstrap circuit turns off the 5V linear regulator and powers the IC from the 5V PWM output voltage if the output is above 4.5V. three signals: the output-voltage error signal with respect to the reference voltage, the current-sense signal, and the slope-compensation ramp (Figure 3). The PWM controller is a direct-summing type, lacking a traditional error amplifier and the phase shift associated with it. This direct-summing configuration approaches ideal cycle-by-cycle control over the output voltage. When SKIP = low, Idle Mode circuitry automatically optimizes efficiency throughout the load current range. Idle Mode dramatically improves light-load efficiency by reducing the effective frequency, which reduces switching losses. It keeps the peak inductor current above 25% of the full current limit in an active cycle, allowing subsequent cycles to be skipped. Idle Mode transitions seamlessly to fixed-frequency PWM operation as load current increases. With SKIP = high, the controller always operates in fixedfrequency PWM mode for lowest noise. Each pulse from the oscillator sets the main PWM latch that turns on the high-side switch for a period determined by the duty factor (approximately VOUT / VIN). As the high-side switch turns off, the synchronous rectifier latch sets; 60ns later, the low-side switch turns on. The low-side switch stays on until the beginning of the next clock cycle. In PWM mode, the controller operates as a fixed-frequency current-mode controller where the duty ratio is set by the input/output voltage ratio. The current-mode feedback system regulates the peak inductor current value as a function of the output-voltage error signal. In continuous-conduction mode, the average inductor current is nearly the same as the peak current, so the circuit acts as a switch-mode transconductance amplifier. This pushes the second output LC filter pole, normally found in a duty-factor-controlled (voltage-mode) PWM, to a higher frequency. To preserve inner-loop stability and eliminate regenerative inductor current "staircasing", a slope-compensation ramp is summed into the main PWM comparator to make the apparent duty factor less than 50%. The MAX1901/MAX1902/MAX1904 use a relatively low loop gain, allowing the use of lower-cost output capacitors. The relative gains of the voltage-sense and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main PWM comparator (Figure 4). The relative gain of the voltage comparator to the current comparator is internally fixed at K = 2:1. The low loop gain results in the 2% typical load-regulation error. The low value of loop gain helps reduce output filter capacitor size and cost by shifting the unity-gain crossover frequency to a lower level. 13 MAX1901/MAX1902/MAX1904 PWM Controller Block The two PWM controllers are nearly identical. The only differences are fixed output settings (3.3V vs. 5V), the VL/CSL5 bootstrap switch connected to the 5V PWM, and SECFB. The heart of each current-mode PWM controller is a multi-input, open-loop comparator that sums ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 INPUT 7V to 24V SHDN CSL5 + 4.5V V+ SYNC MAX1902 ON/OFF 5V ALWAYS ON VL 5V LINEAR REG 12V LINEAR REG 12OUT IN VDD 13V BST5 DH5 VL 3.3V PWM LOGIC 333kHz TO 500kHz OSC 5V PWM LOGIC LX5 VL DL5 PGND 5V RAW 15V 12V REF BST3 DH3 3.3V LX3 DL3 2.5V REF SECFB + - OV/UV FAULT REF LPF 50kHz 1.75V 2.68V REF LPF 50kHz + + 0.6V VL TIMER 2.6V SEQ 1V GND RESET + + 0.6V REF + CSH3 CSL3 CSH5 CSL5 2.388V OUTPUTS UP + R1 FB3 R2 R3 FB5 R4 + TIME/ON5 RUN/ON3 Figure 2. MAX1902 Functional Diagram 14 ______________________________________________________________________________________ + POWER-ON SEQUENCE LOGIC + - 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 CSH_ 1X CSL_ REF FROM FEEDBACK DIVIDER MAIN PWM COMPARATOR R Q S LEVEL SHIFT BST_ DH_ LX_ SLOPE COMP OSC 30mV SKIP DAC CURRENT LIMIT SHOOTTHROUGH CONTROL CK SHDN COUNTER SOFT-START SYNCHRONOUS RECTIFIER CONTROL R -100mV S VL Q LEVEL SHIFT DL_ PGND REF 0.75s SINGLE-SHOT SECFB Figure 3. PWM Controller Functional Block Diagram ______________________________________________________________________________________ 15 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Table 3. SKIP PWM Table SKIP Low Low High High LOAD CURRENT Light Heavy Light Heavy MODE Idle PWM PWM PWM VL R1 R2 TO PWM LOGIC UNCOMPENSATED HIGH-SPEED LEVEL TRANSLATOR AND BUFFER OUTPUT DRIVER I1 I2 I3 VBIAS DESCRIPTION Pulse-skipping, supply current = 250A at VIN =12V, discontinuous inductor Constant-frequency PWM continuous-inductor current Constant-frequency PWM continuous-inductor current Constant-frequency PWM continuous-inductor current FB_ REF CSH_ CSL_ SLOPE COMPENSATION Figure 4. Main PWM Comparator Block Diagram The output filter capacitors (Figure1, C1 and C2) set a dominant pole in the feedback loop that must roll off the loop gain to unity before encountering the zero introduced by the output capacitor's parasitic resistance (ESR) (see the Design Procedure section). A 50kHz pole-zero cancellation filter provides additional rolloff above the unity-gain crossover. This internal 50kHz low-pass compensation filter cancels the zero due to filter capacitor ESR. The 50kHz filter is included in the loop in both fixed-output and adjustable-output modes. chronous switch is turned off as the inductor current falls through zero. The synchronous rectifier works under all operating conditions, including Idle Mode. The SECFB signal further controls the synchronous switch timing in order to improve multiple-output cross-regulation (see the Secondary Feedback Regulation Loop section). Internal VL and REF Supplies An internal regulator produces the 5V supply (VL) that powers the PWM controller, logic, reference, and other blocks within the IC. This 5V low-dropout linear regulator supplies up to 25mA for external loads, with a reserve of 25mA for supplying gate-drive power. Bypass VL to GND with 4.7F. Important: Ensure that V L does not exceed 6V. Measure VL with the main output fully loaded. If it is pumped above 5.5V, either excessive boost-diode capacitance or excessive ripple at V+ is the probable cause. Use only small-signal diodes for the boost circuit (10mA to 100mA Schottky or 1N4148 are preferred), and bypass V+ to PGND with 4.7F directly at the package pins. Synchronous Rectifier Driver (DL) Synchronous rectification reduces conduction losses in the rectifier by shunting the normal Schottky catch diode with a low-resistance MOSFET switch. Also, the synchronous rectifier ensures proper startup of the boost gate-driver circuit. If the circuit is operating in continuous-conduction mode, the DL drive waveform is simply the complement of the DH high-side drive waveform (with controlled dead time to prevent cross-conduction or "shoot through"). In discontinuous (light-load) mode, the syn16 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers The 2.5V reference (REF) is accurate to 2% over temperature, making REF useful as a precision system reference. Bypass REF to GND with 1F minimum. REF can supply up to 5mA for external loads. (Bypass REF with a minimum 1F/mA reference load current.) However, if extremely accurate specifications for both the main output voltages and REF are essential, avoid loading REF more than 100A. Loading REF reduces the main output voltage slightly, because of the reference load-regulation error. When the 5V main output voltage is above 4.5V, an internal P-channel MOSFET switch connects CSL5 to VL, while simultaneously shutting down the VL linear regulator. This action bootstraps the IC, powering the internal circuitry from the output voltage, rather than through a linear regulator from the battery. Bootstrapping reduces power dissipation due to gate charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a much less efficient linear regulator. current to support the full load current, while components must be designed to withstand continuouscurrent stresses of 120mV/R1. For breadboarding or for very-high-current applications, it may be useful to wire the current-sense inputs with a twisted pair, rather than PC traces. (This twisted pair need not be special; two pieces of wire-wrap wire twisted together is sufficient.) This reduces the possible noise picked up at CSH_ and CSL_, which can cause unstable switching and reduced output current. The CSL5 input also serves as the IC's bootstrap supply input. Whenever VCSL5 > 4.5V, an internal switch connects CSL5 to VL. MAX1901/MAX1902/MAX1904 Oscillator Frequency and Synchronization (SYNC) The SYNC input controls the oscillator frequency. Low selects 333kHz; high selects 500kHz. SYNC can also be used to synchronize with an external 5V CMOS or TTL clock generator. SYNC has a guaranteed 400kHz to 583kHz capture range. A high-to-low transition on SYNC initiates a new cycle. 500kHz operation optimizes the application circuit for component size and cost. 333kHz operation provides increased efficiency, lower dropout, and improved load-transient response at low input-output voltage differences (see the Low-Voltage Operation section). Boost High-Side Gate-Drive Supply (BST3 and BST5) Gate-drive voltage for the high-side N-channel switches is generated by a flying-capacitor boost circuit (Figure 2). The capacitor between BST_ and LX_ is alternately charged from the VL supply and placed parallel to the high-side MOSFET's gate-source terminals. On startup, the synchronous rectifier (low-side MOSFET) forces LX_ to 0V and charges the boost capacitors to 5V. On the second half-cycle, the SMPS turns on the high-side MOSFET by closing an internal switch between BST_ and DH_. This provides the necessary enhancement voltage to turn on the high-side switch, an action that "boosts" the 5V gate-drive signal above the battery voltage. Ringing at the high-side MOSFET gate (DH3 and DH5) in discontinuous-conduction mode (light loads) is a natural operating condition. It is caused by residual energy in the tank circuit, formed by the inductor and stray capacitance at the switching node, LX. The gate-drive negative rail is referred to LX, so any ringing there is directly coupled to the gate-drive output. Shutdown Mode Holding SHDN low puts the IC into its 4A shutdown mode. SHDN is logic input with a threshold of about 1V (the VTH of an internal N-channel MOSFET). For automatic startup, bypass SHDN to GND with a 0.01F capacitor and connect it to V+ through a 220k resistor. Power-Up Sequencing and ON/OFF Controls Startup is controlled by RUN/ON3 and TIME/ON5 in conjunction with SEQ. With SEQ tied to REF, the two control inputs act as separate ON/OFF controls for each supply. With SEQ tied to VL or GND, RUN/ON3 becomes the master ON/OFF control input and TIME/ON5 becomes a timing pin, with the delay between the two supplies determined by an external capacitor. The delay is approximately 800s/nF. The 3.3V supply powers up first if SEQ is tied to VL, and the 5V supply is first if SEQ is tied to GND. When driving TIME/ON5 as a control input with external logic, always place a resistor (>1k) in series with the input. This prevents possible crowbar current due to the internal discharge pulldown transistor, which turns on in standby mode and momentarily at the first power-up or in shutdown mode. 17 Current-Limiting and Current-Sense Inputs (CSH and CSL) The current-limit circuit resets the main PWM latch and turns off the high-side MOSFET switch whenever the voltage difference between CSH and CSL exceeds 100mV. This limiting is effective for both current flow directions, putting the threshold limit at 100mV. The tolerance on the positive current limit is 20%, so the external low-value sense resistor (R1) must be sized for 80mV/ IPEAK, where IPEAK is the required peak-inductor ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 RESET Power-Good Voltage Monitor The power-good monitor generates a system RESET signal. At first power-up, RESET is held low until both the 3.3V and 5V SMPS outputs are in regulation. At this point, an internal timer begins counting oscillator pulses, and RESET continues to be held low until 32,000 cycles have elapsed. After this timeout period (64ms at 500kHz or 96ms at 333kHz), RESET is actively pulled up to VL. If SEQ is tied to REF (for separate ON3/ON5 controls), only the 3.3V SMPS is monitored--the 5V SMPS is ignored. Output Overvoltage Protection (MAX1901/MAX1902) Both SMPS outputs are monitored for overvoltage. If either output is more than 7% above the nominal regulation point, both low-side gate drivers (DL_) are latched high until SHDN or RUN/ON3 is toggled, or until V+ power is cycled below 1V. This action turns on the synchronous rectifiers with 100% duty, in turn rapidly discharging the output capacitors and forcing both SMPS outputs to ground. The DL outputs are also kept high whenever the corresponding SMPS is disabled, and in shutdown if VL is sustained. Discharging the output capacitor through the main inductor causes the output to momentarily go below GND. Clamp this negative pulse with a back-biased 1A Schottky diode across the output capacitor (Figure 1). To ensure overvoltage protection on initial power-up, connect signal diodes from both output voltages to VL (cathodes to VL) to eliminate the VL power-up delay. This circuitry protects the load from accidental overvoltage caused by a short circuit across the high-side power MOSFETs. This scheme relies on the presence of a fuse, in series with the battery, which is blown by the resulting crowbar current. Note that the overvoltage circuitry will interfere with external keep-alive supplies that hold up the outputs (such as lithium backup or hotswap power supplies); in such cases, the MAX1904 should be used. Output Undervoltage Shutdown Protection (MAX1901/MAX1902) The output undervoltage lockout circuit is similar to foldback current limiting, but employs a timer rather than a variable current limit. Each SMPS has an undervoltage protection circuit that is activated 6144 clock cycles after the SMPS is enabled. If either SMPS output is under 70% of the nominal value, both SMPSs are latched off and their outputs are clamped to ground by the synchronous rectifier MOSFETs (see the Output Overvoltage Protection section). They won't restart until SHDN or RUN/ON3 is toggled, or until V+ power is cycled below 1V. Note that undervoltage protection can make prototype troubleshooting difficult, since you have only 12ms or 18ms to figure out what might be wrong with the circuit before both SMPSs are latched off. In extreme cases, it may be useful to substitute the MAX1904 into the prototype breadboard until the prototype is working properly. Low-Noise Operation (PWM Mode) PWM mode (SKIP = high) minimizes RF and audio interference in noise-sensitive applications (such as hi-fi multimedia-equipped systems), cellular phones, RF communicating computers, and electromagnetic pen entry systems. See the summary of operating modes in Table 2. SKIP can be driven from an external logic signal. Table 4. Operating Modes SHDN Low High High High High High High High High SEQ X REF REF REF REF GND GND VL VL RUN/ON3 X Low High Low High Low High Low High TIME/ON5 X Low Low High High Timing Capacitor Timing Capacitor Timing Capacitor Timing Capacitor MODE Shutdown Standby Run Run Run Standby Run Standby Run DESCRIPTION All circuit blocks turned off. Supply current = 4A. Both SMPSs off. Supply current = 30A. 3.3V SMPS enabled/5V off. 5V SMPS enabled/3.3V off. Both SMPSs enabled. Both SMPSs off. Supply current = 30A. Both SMPSs enabled. 5V enabled before 3.3V. Both SMPSs off. Supply current = 30A. Both SMPSs enabled. 3.3V enabled Before 5V. 18 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Interference due to switching noise is reduced in PWM mode by ensuring a constant switching frequency, thus concentrating the emissions at a known frequency outside the system audio or IF bands. Choose an oscillator frequency for which switching frequency harmonics don't overlap a sensitive frequency band. If necessary, synchronize the oscillator to a tight-tolerance external clock generator. To extend the output-voltage regulation range, constant operating frequency is not maintained under overload or dropout conditions (see the Dropout Operation section). PWM mode (SKIP = high) forces two changes upon the PWM controllers. First, it disables the minimum-current comparator, ensuring fixed-frequency operation. Second, it changes the detection threshold for reverse current limit from 0 to -100mV, allowing the inductor current to reverse at light loads. This results in fixed-frequency operation and continuous inductor-current flow. This eliminates discontinuous-mode inductor ringing and improves cross regulation of transformer-coupled multiple-output supplies, particularly in circuits that don't use additional secondary regulation via SECFB or VDD. In most applications, tie SKIP to GND to minimize quiescent supply current. VL supply current with SKIP high is typically 30mA, depending on external MOSFET gate capacitance and switching losses. action can continue until three off-time periods are skipped, effectively dividing the clock frequency by as much as four. The typical PWM minimum off-time is 300ns, regardless of the operating frequency. Lowering the operating frequency raises the maximum duty factor above 97%. MAX1901/MAX1902/MAX1904 Adjustable-Output Feedback (Dual Mode FB) Fixed, preset output voltages are selected when FB_ is connected to ground. Adjusting the main output voltage with external resistors is simple for any of the MAX1901/MAX1902/MAX1904, through resistor dividers connected to FB3 and FB5 (Figure 2). Calculate the output voltage with the following formula: VOUT = VREF (1 + R1 / R2) where VREF = 2.5V nominal. The nominal output should be set approximately 1% or 2% high to make up for the MAX1901/MAX1902/ MAX1904 -2% typical load-regulation error. For example, if designing for a 3.0V output, use a resistor ratio that results in a nominal output voltage of 3.05V. This slight offsetting gives the best possible accuracy. Recommended normal values for R2 range from 5k to 100k. To achieve a 2.5V nominal output, simply connect FB_ directly to CSL_. Remote output-voltage sensing, while not possible in fixed-output mode due to the combined nature of the voltage-sense and current-sense inputs (CSL3 and CSL5), is easy to do in adjustable mode by using the top of the external resistor-divider as the remote sense point. When using adjustable mode, it is a good idea to always set the "3.3V output" to a lower voltage than the "5V output." The 3.3V output must always be less than VL, so that the voltage on CSH3 and CSL3 is within the common-mode range of the current-sense inputs. While VL is nominally 5V, it can be as low as 4.7V when linearly regulating, and as low as 4.2V when automatically bootstrapped to CSH5. Internal Digital Soft-Start Circuit Soft-start allows a gradual increase of the internal current-limit level at startup to reduce input surge currents. Both SMPSs contain internal digital soft-start circuits, each controlled by a counter, a digital-to-analog converter (DAC), and a current-limit comparator. In shutdown or standby mode, the soft-start counter is reset to zero. When an SMPS is enabled, its counter starts counting oscillator pulses, and the DAC begins incrementing the comparison voltage applied to the currentlimit comparator. The DAC output increases from 0 to 100mV in five equal steps as the count increases to 512 clocks. As a result, the main output capacitor charges up relatively slowly. The exact time of the output rise depends on output capacitance and load current, and is typically 600s with a 500kHz oscillator. Dropout Operation Dropout (low input-output differential operation) is enhanced by stretching the clock pulse width to increase the maximum duty factor. The algorithm follows: If the output voltage (VOUT) drops out of regulation without the current limit having been reached, the SMPS skips an off-time period (extending the on-time). At the end of the cycle, if the output is still out of regulation, the SMPS skips another off-time period. This Secondary Feedback Regulation Loop (SECFB or VDD) A flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the primary output is lightly loaded or when there is a low input-output differential voltage. If VDD or SECFB falls below its regulation threshold, the low-side switch is turned on for an extra 0.75s. This reverses the induc19 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 tor (primary) current, pulling current from the output filter capacitor and causing the flyback transformer to operate in forward mode. The low impedance presented by the transformer secondary in forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing VDD or SECFB back into regulation. The secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. In this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage. A linear post-regulator may still be needed to meet strict output-accuracy specifications. MAX1902 has a VDD pin that regulates at a fixed 13.5V, set by an internal resistor-divider. The MAX1901/ MAX1904 have an adjustable secondary-output voltage set by an external resistor-divider on SECFB (Figure 5). Ordinarily, the secondary regulation point is set 5% to 10% below the voltage normally produced by the flyback effect. For example, if the output voltage as determined by turns ratio is 15V, set the feedback resistor ratio to produce 13.5V. Otherwise, the SECFB one-shot might be triggered unintentionally, unnecessarily increasing supply current and output noise. 12V Linear Regulator Output (MAX1902) The MAX1902 includes a 12V linear regulator output capable of delivering 120mA of output current. Typically, greater current is available at the expense of output accuracy. If an accurate output of more than 120mA is needed, an external pass transistor can be added. The circuit in Figure 6 delivers more than 200mA. Total output current is constrained by the V+ input voltage and the transformer primary load (see Maximum VDD Output Current vs. Input Voltage graphs in the Typical Operating Characteristics). Design Procedure The three predesigned 3V/5V standard application circuits (Figure 1 and Table 1) contain ready-to-use solutions for common application needs. Also, one standard flyback transformer circuit supports the 12OUT linear regulator in the Applications Information section. Use the following design procedure to optimize these basic schematics for different voltage or current requirements. But before beginning a design, firmly establish the following: Maximum Input (Battery) Voltage, VIN(MAX). This value should include the worst-case conditions, such as noload operation when a battery charger or AC adapter is R2 SECFB 1-SHOT TRIG 2.5V REF V+ 12OUT 0.1F VDD 2N3906 0.1F 10 12V OUTPUT 200mA 10F R1 POSITIVE SECONDARY OUTPUT DH_ MAX1902 MAX1901 MAX1904 DL_ MAIN OUTPUT V+ 0.1F VDD OUTPUT DH_ 2.2F MAIN OUTPUT +VTRIP = VREF R1 (1 + ---) R2 WHERE VREF (NOMINAL) = 2.5V DL_ Figure 5. Adjusting the Secondary Output Voltage with SECFB 20 Figure 6. Increased 12V Linear Regulator Output Current ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers connected but no battery is installed. VIN(MAX) must not exceed 30V. Minimum Input (Battery) Voltage, VIN(MIN).This should be taken at full load under the lowest battery conditions. If VIN(MIN) is less than 4.2V, use an external circuit to externally hold VL above the VL undervoltage lockout threshold. If the minimum input-output difference is less than 1.5V, the filter capacitance required to maintain good AC load regulation increases (see the Low-Voltage Operation section). LIR = ratio of AC to DC inductor current, typically 0.3; should be >0.15 The nominal peak-inductor current at full load is 1.15 IOUT if the above equation is used; otherwise, the peak current can be calculated by: IPEAK = ILOAD + MAX1901/MAX1902/MAX1904 (VOUT (VIN(MAX) - VOUT ) 2 x f x L x VIN(MAX) Inductor Value The exact inductor value isn't critical and can be freely adjusted to make trade-offs between size, cost, and efficiency. Lower inductor values minimize size and cost, but reduce efficiency due to higher peak-current levels. The smallest inductor is achieved by lowering the inductance until the circuit operates at the border between continuous and discontinuous mode. Further reducing the inductor value below this crossover point results in discontinuous-conduction operation even at full load. This helps lower output-filter capacitance requirements, but efficiency suffers due to high I2R losses. On the other hand, higher inductor values mean greater efficiency, but resistive losses due to extra wire turns will eventually exceed the benefit gained from lower peak-current levels. Also, high inductor values can affect load-transient response (see the VSAG equation in the Low-Voltage Operation section). The equations that follow are for continuous-conduction operation, since the MAX1901/MAX1902/MAX1904 are intended mainly for high-efficiency, battery-powered applications. Discontinuous conduction doesn't affect normal idle-mode operation. Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant (LIR) which is the ratio of inductor peak-topeak AC current to DC load current. A higher LIR value allows smaller inductance, but results in higher losses and higher ripple. A good compromise between size and losses is found at a 30% ripple-current to load-current ratio (LIR = 0.3), which corresponds to a peakinductor current 1.15 times higher than the DC load current. L= where: VOUT VIN(MAX) - VOUT The inductor's DC resistance should be low enough that RDC IPEAK < 100mV, as it is a key parameter for efficiency performance. If a standard off-the-shelf inductor is not available, choose a core with an LI2 rating greater than L IPEAK2 and wind it with the largest-diameter wire that fits the winding area. Ferrite core material is strongly preferred. Shielded-core geometries help keep noise, EMI, and switching-waveform jitter low. Current-Sense Resistor Value The current-sense resistor value is calculated according to the worst-case low current-limit threshold voltage (from the Electrical Characteristics) and the peak inductor current: RSENSE = 80mV IPEAK Use IPEAK from the second equation in the Inductor Value section. Use the calculated value of RSENSE to size the MOSFET switches and specify inductor saturation-current ratings according to the worst-case high current-limit threshold voltage: IPEAK(MAX) = 120mV RSENSE Low-inductance resistors, such as surface-mount metal-film, are recommended. Input-Capacitor Value The input filter capacitor is usually selected according to input ripple current requirements and voltage rating, rather than capacitor value. Ceramic capacitors or Sanyo OS-CON capacitors are typically used to handle the power-up surge-currents, especially when connecting to robust AC adapters or low-impedance batteries. RMS input ripple current (IRMS) is determined by the input voltage and load current, with the worst case occurring at VIN = 2 VOUT: VIN(MAX) x f x IOUT x LIR ( ) f = switching frequency, normally 333kHz or 500kHz IOUT = maximum DC load current ______________________________________________________________________________________ 21 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 IRMS = ILOAD x VOUT (VIN - VOUT ) VIN scope won't quite sync up. Technically speaking, this jitter (usually harmless) is unstable operation, since the duty factor varies slightly. As capacitors with higher ESRs are used, the jitter becomes more pronounced, and the load-transient output-voltage waveform starts looking ragged at the edges. Eventually, the load-transient waveform has enough ringing on it that the peak noise levels exceed the allowable output-voltage tolerance. Note that even with zero phase margin and gross instability present, the output-voltage noise never gets much worse than IPEAK RESR (under constant loads). The output-voltage ripple is usually dominated by the filter capacitor's ESR, and can be approximated as IRIPPLE RESR. There is also a capacitive term, so the full equation for ripple in continuous-conduction mode is V NOISE (p-p) = I RIPPLE [R ESR + 1/(2 f COUT)]. In idle mode, the inductor current becomes discontinuous, with high peaks and widely spaced pulses, so the noise can actually be higher at light load (compared to full load). In idle mode, calculate the output ripple as follows: VNOISE(P-P) = 0.025 x RESR + RSENSE 0.0003 x L x [1/ VOUT + 1/(VIN - VOUT )] RSENSE2 x COUT Therefore, when VIN is 2 x VOUT: I IRMS = LOAD 2 Bypassing V+ Bypass the V+ input with a 4.7F tantalum capacitor paralleled with a 0.1F ceramic capacitor, close to the IC. A 10 series resistor to VIN is also recommended. Bypassing VL Bypass the VL output with a 4.7F tantalum capacitor paralleled with a 0.1F ceramic capacitor, close to the device. Output-Filter Capacitor Value The output-filter capacitor values are generally determined by the ESR and voltage-rating requirements, rather than actual capacitance requirements for loop stability. In other words, the low-ESR electrolytic capacitor that meets the ESR requirement usually has more output capacitance than is required for AC stability. Use only specialized low-ESR capacitors intended for switchingregulator applications, such as AVX TPS, Sanyo POSCAP, or Kemet T510. To ensure stability, the capacitor must meet both minimum capacitance and maximum ESR values as given in the following equations: COUT > VREF (1 + VOUT / VIN(MIN) ) VOUT x RSENSE x f R x VOUT RESR < SENSE VREF These equations are worst case, with 45 of phase margin to ensure jitter-free, fixed-frequency operation and provide a nicely damped output response for zero to full-load step changes. Some cost-conscious designers may wish to bend these rules with less-expensive capacitors, particularly if the load lacks large step changes. This practice is tolerable if some bench testing over temperature is done to verify acceptable noise and transient response. No well-defined boundary exists between stable and unstable operation. As phase margin is reduced, the first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the 22 Transformer Design (for Auxiliary Outputs Only) Buck-plus-flyback applications, sometimes called "coupled-inductor" topologies, need a transformer to generate multiple output voltages. Performing the basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary to calculate the current-sense resistor and primary inductance. However, extremes of low input-output differentials, widely different output loading levels, and high turns ratios can complicate the design due to parasitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. For examples of what is possible with real world transformers, see the Maximum V DD Output Current vs. Input Voltage graph in the Typical Operating Characteristics. Power from the main and secondary outputs is combined to get an equivalent current referred to the main output voltage (see the Inductor Value section for parameter definitions). Set the current-sense resistor value at 80mV / ITOTAL. ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers PTOTAL = The sum of the output power from all outputs ITOTAL = PTOTAL / VOUT = The equivalent output current referred to VOUT LPRIMARY = VOUT (VIN(MAX) - VOUT ) VIN(MAX) x f x ITOTAL x LIR VSEC + VFWD VOUT(MIN) + VRECT + VSENSE distributed between Q1 and Q2 according to duty factor (see the following equations). Generally, switching losses affect only the upper MOSFET, since the Schottky rectifier clamps the switching node in most cases before the synchronous rectifier turns on. Gate charge losses are dissipated by the driver and don't heat the MOSFET. Calculate the temperature rise according to package thermal-resistance specifications to ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case dissipation for the high-side MOSFET occurs at both extremes of input voltage, and the worst-case dissipation for the low-side MOSFET occurs at maximum input voltage: PDupperFET = ILOAD2 x RDS(ON) x DUTY + VIN x ILOAD x f x VIN x CRSS + 20ns I GATE PDupperFET = ILOAD2 x RDS(ON) x (1- DUTY) DUTY = (VOUT + VQ2 ) / (VIN - VQ1) MAX1901/MAX1902/MAX1904 Turns Ratio N = where: VSEC = the minimum required rectified sec ondary output voltage VFWD = the forward drop across the secondary rectifier VOUT(MIN) = the minimum value of the main out put voltage (from the Electrical Characteristics tables) VRECT = the on-state voltage drop across the synchronous rectifier MOSFET VSENSE = the voltage drop across the sense resistor In positive-output applications, the transformer secondary return is often referred to the main output voltage, rather than to ground, to reduce the needed turns ratio. In this case, the main output voltage must first be subtracted from the secondary voltage to obtain VSEC. where: On-state voltage drop VQ_ = ILOAD RDS(ON) CRSS = MOSFET reverse transfer capacitance IGATE = DH driver peak output current capability (1A typ) 20ns = DH driver inherent rise/fall time Under output short-circuit, the MAX1904 synchronous rectifier MOSFET suffers extra stress because its duty factor can increase to greater than 0.9. It may need to be oversized to tolerate a continuous DC short circuit. During short circuit, the MAX1901/MAX1902's output undervoltage shutdown protects the synchronous rectifier under output short-circuit conditions. To reduce EMI, add a 0.1F ceramic capacitor from the high-side switch drain to the low-side switch source. Rectifier Clamp Diode The rectifier diode is a clamp across the low-side MOSFET that catches the negative inductor swing during the 60ns dead time between turning one MOSFET off and each low-side MOSFET on. The latest generations of MOSFETs incorporate a high-speed Schottky diode, which serves as an adequate clamp diode. For MOSFETs without integrated Schottky diodes, place a Schottky diode in parallel with the low-side MOSFET. Selecting Other Components MOSFET Switches The high-current N-channel MOSFETs must be logiclevel types with guaranteed on-resistance specifications at V GS = 4.5V. Lower gate threshold specifications are better (i.e., 2V max rather than 3V max). Drain-source breakdown voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating factor. The best MOSFETs will have the lowest on-resistance per nanocoulomb of gate charge. Multiplying RDS(ON) QG provides a good figure for comparing various MOSFETs. Newer MOSFET process technologies with dense cell structures generally perform best. The internal gate drivers tolerate >100nC total gate charge, but 70nC is a more practical upper limit to maintain best switching times. In high-current applications, MOSFET package power dissipation often becomes a dominant design factor. I2R power losses are the greatest heat contributor for both high-side and low-side MOSFETs. I2R losses are ______________________________________________________________________________________ 23 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Use a Schottky diode with a DC current rating equal to one third of the load current. The Schottky diode's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. Boost-Supply Diode A signal diode such as a 1N4148 works well in most applications. If the input voltage can go below +6V, use a small (20mA) Schottky diode for slightly improved efficiency and dropout characteristics. Don't use large power diodes, such as 1N5817 or 1N4001, since high junction capacitance can pump up VL to excessive voltages. Rectifier Diode (Transformer Secondary Diode) The secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60V, which usually rules out most Schottky rectifiers. Common silicon rectifiers, such as the 1N4001, are also prohibited because they are too slow. This often makes fast silicon rectifiers such as the MURS120 the only choice. The flyback voltage across the rectifier is related to the VIN - VOUT difference, according to the transformer turns ratio: VFLYBACK = VSEC + (VIN - VOUT) N where: N = the transformer turns ratio SEC/PRI V SEC = the maximum secondary DC output voltage VOUT = the primary (main) output voltage Subtract the main output voltage (VOUT) from VFLYBACK in this equation if the secondary winding is returned to VOUT and not to ground. The diode reversebreakdown rating must also accommodate any ringing due to leakage inductance. The rectifier diode's current rating should be at least twice the DC load current on the secondary output. Low-Voltage Operation Low input voltages and low input-output differential voltages each require extra care in their design. Low absolute input voltages can cause the VL linear regulator to enter dropout and eventually shut itself off. Low input voltages relative to the output (low VIN - VOUT differential) can cause bad load regulation in multi-output flyback applications (see the design equations in the Transformer Design section). Also, low VIN - VOUT differentials can also cause the output voltage to sag when the load current changes abruptly. The amplitude of the sag is a function of inductor value and maximum duty factor (an 24 Electrical Characteristics parameter, 97% guaranteed over temperature at f = 333kHz), as follows: VSAG = 2 x COUT ISTEP 2 x L x (VIN(MIN) x DMAX - VOUT ) The cure for low-voltage sag is to increase the output capacitor's value. Take a 333kHz/6A application circuit as an example, at VIN = +5.5V, VOUT = +5V, L = 6.7H, f = 333kHz, ISTEP = 3A (half-load step), a total capacitance of 470F keeps the sag less than 200mV. The capacitance is higher than that shown in the Typical Application Circuit because of the lower input voltage. Note that only the capacitance requirement increases, and the ESR requirements don't change. Therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-ESR capacitor. Applications Information Heavy-Load Efficiency Considerations The major efficiency-loss mechanisms under loads are, in the usual order of importance: * P(I2R) = I2R losses * P(tran) = transition losses * P(gate) = gate-charge losses * P(diode) = diode-conduction losses * P(cap) = input capacitor ESR losses * P(IC) = losses due to the IC's operating supply current Inductor core losses are fairly low at heavy loads because the inductor's AC current component is small. Therefore, they aren't accounted for in this analysis. Ferrite cores are preferred, especially at 300kHz, but powdered cores, such as Kool-Mu, can work well: Efficiency = POUT/PIN 100% = POUT/(POUT + PTOTAL) 100% PTOTAL = P(I2R) + P(tran) + P(gate) + P(diode) + P(cap) + P(IC) P (I2R) = ILOAD2 x (RDC + RDS(ON) + RSENSE) where RDC is the DC resistance of the coil, RDS(ON) is the MOSFET on-resistance, and RSENSE is the currentsense resistor value. The RDS(ON) term assumes identical MOSFETs for the high-side and low-side switches: because they time-share the inductor current. If the MOSFETs aren't identical, their losses can be estimated by averaging the losses according to duty factor. ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Table 5. Low-Voltage Troubleshooting Chart SYMPTOM Sag or droop in VOUT under step-load change Dropout voltage is too high (VOUT follows VIN as VIN decreases) Unstable--jitters between different duty factors and frequencies CONDITION Low VIN - VOUT differential, <1.5V ROOT CAUSE Limited inductor-current slew rate per cycle. SOLUTION Increase bulk output capacitance per formula (see the Low-Voltage Operation section). Reduce inductor value. Reduce operation to 333kHz. Reduce MOSFET on-resistance and coil DCR. Low VIN - VOUT differential, <1V Maximum duty-cycle limits exceeded. Low VIN - VOUT differential, <0.5V Low VIN - VOUT differential, VIN < 1.3 VOUT(MAIN) Low input voltage, <5V Low input voltage, <4.5V Normal function of internal lowdropout circuitry. Not enough duty cycle left to initiate forward-mode operation. Small AC current in primary can't store energy for flyback operation. VL linear regulator is going into dropout and isn't providing good gate-drive levels. VL output is so low that it hits the VL UVLO threshold. Increase the minimum input voltage or ignore. Reduce operation to 333kHz. Reduce secondary impedances; use a Schottky diode, if possible. Stack secondary winding on the main output. Use a small 20mA Schottky diode for boost diode. Supply VL from an external source. Supply VL from an external source other than VIN, such as the system 5V supply. Secondary output won't support a load Poor efficiency Won't start under load or quits before battery is completely dead P(tran) = VIN x ILOAD x fx 3 x 2 where tD is the diode-conduction time (120ns typ) and VFWD is the forward voltage of the diode. This power is dissipated in the MOSFET body diode if no external Schottky diode is used: P(cap) = (IRMS)2 x RESR where IRMS is the input ripple current as calculated in the Design Procedure and Input-Capacitor Value sections. [(VIN x CRSS / IGATE ) - 20ns] where CRSS is the reverse transfer capacitance of the high-side MOSFET (a data sheet parameter), IGATE is the DH gate-driver peak output current (1.5A typical), and 20ns is the rise/fall time of the DH driver (20ns typ). P(gate) = QG f VL where VL is the internal-logic-supply voltage (5V), and QG is the sum of the gate-charge values for low-side and high-side switches. For matched MOSFETs, QG is twice the data sheet value of an individual MOSFET. If VOUT is set to less than 4.5V, replace VL in this equation with V BATT . In this case, efficiency can be improved by connecting VL to an efficient 5V source, such as the system 5V supply: P(diode) = ILOAD VFWD tD f Light-Load Efficiency Considerations Under light loads, the PWM operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. This makes the inductor current's AC component high compared to the load current, which increases core losses and I2R losses in the output filter capacitors. For best light-load efficiency, use MOSFETs with moderate gate-charge levels, and use ferrite, MPP, or other low-loss core material. ______________________________________________________________________________________ 25 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Lossless-Inductor Current-Sensing The DC resistance (DCR) of the inductor can be used to sense inductor current to improve the efficiency and to reduce the cost by eliminating the sense resistor. Figure 7 shows the sense circuit, where L is the inductance, RL is the inductor DCR, RS, and CS form an RC low-pass sense network. If the time constant of the inductor is equal to that of the sense network, i.e.: L = RSCS RL then the voltage across CS becomes VS = RL x IL where IL is the inductor current. Determine the required sense-resistor value using the equation given in the Current-Sense Resistor Value section. Choose an inductor with DCR equal or greater than the sense resistor value. If the DCR is greater than the sense-resistor value, use a divider to scale down the voltage. Use the maximum inductance and minimum DCR to get the maximum possible inductor time constant. Select RS and CS so that the maximum sense network time constant is equal or greater than the maximum inductor time constant. Reduced Output Capacitance Application In applications where higher output ripple is acceptable, lower output capacitance or higher ESR output capacitors can be used. In such cases, cycle-by-cycle stability is maintained by adding feedforward compensation to offset for the increased output ESR. Figure 8 shows the addition of the feedforward compensation circuit. CFB provides noise filtering, RFF is the feedforward resistor and C LX provides DC blocking. Use 100pF for CFB and CLX. Select RFF according to the equation below: RFF 4 x R3 x L x f ESR Set the value for RFF close to the calculation. Do not make RFF too small as that will introduce too much feedforward, possibly causing an overvoltage to be seen at the feedback pin, and changing the mode of operation to a voltage mode. PC Board Layout Considerations Good PC board layout is required in order to achieve specified noise, efficiency, and stability performance. The PC board layout artist must be given explicit instructions, preferably a pencil sketch showing the placement of power-switching components and highcurrent routing. A ground plane is essential for optimum VIN DH_ CIN INDUCTOR L LX_ RS CS RL VOUT DH_ CSL_ CSH_ LX_ L RSENSE VOUT R3 VIN CIN MAX1901 MAX1902 MAX1904 CSH_ COUT CSL_ MAX1901 MAX1902 MAX1904 FB_ DL_ CLX RFF CFB COUT R4 DL_ Figure 7. Lossless Inductor Current Sensing Figure 8. Adding Feedforward Compensation 26 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers performance. In most applications, the circuit will be located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections, the bottom layer for quiet connections (REF, SS, GND), and the inner layers for an uninterrupted ground plane. Use the following stepby-step guide: 1) Place the high-power components (Figure 1, C1, C3, C4, Q1, Q2, L1, and R1) first, with their grounds adjacent. * Priority 1: Minimize current-sense resistor trace lengths and ensure accurate current sensing with Kelvin connections (Figure 9). * Priority 2: Minimize ground trace lengths in the high-current paths (discussed below). * Priority 3: Minimize other trace lengths in the high current paths. Use >5mm-wide traces CIN to high-side MOSFET drain: 10mm max length Rectifier diode cathode to low-side MOSFET: 5mm max length LX node (MOSFETs, rectifier cathode, inductor): 15mm max length Ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide filled zone of top-layer copper so they don't go through vias. The resulting top layer "subground-plane" is connected to the normal inner-layer ground plane at the output ground terminals, which ensures that the IC's analog ground is sensing at the supply's output terminals without interference from IR drops MAX1901/MAX1902/MAX1904 HIGH-CURRENT PATH SENSE RESISTOR MAX1901/MAX1902/MAX1904 Figure 9. Kelvin Connections for the Current-Sense Resistors and ground noise. Other high-current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all PC board layout problems. 2) Place the IC and signal components. Keep the main switching nodes (LX nodes) away from sensitive analog components (current-sense traces and REF capacitor). Place the IC and analog components on the opposite side of the board from the powerswitching node. Important: the IC must be no more than 10mm from the current-sense resistors. Keep the gate-drive traces (DH_, DL_, and BST_) shorter than 20mm and route them away from CSH_, CSL_, and REF. 3) Use a single-point star ground where the input ground trace, power ground (sub-ground-plane), and normal ground plane meet at the supply's output ground terminal. Connect both IC ground pins and all IC bypass capacitors to the normal ground plane. ______________________________________________________________________________________ 27 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 TO 3.3V OUTPUT INPUT 6.5V TO 28V C3 10 C4 * * TO 5V OUTPUT 4.7F 0.1F 22 6 21 4 5 D2 18 16 Q3 R2 D5 2.2F 0.1F 4.7F 5V ALWAYS ON V+ SYNC VL ON/OFF 23 SHDN 12OUT VDD 25 Q1 27 3.3V OUTPUT (3A) C1 L1 R1 0.1F 26 0.1F 24 Q2 1N5819 1 2 3 28 7 CSH3 CSL3 FB3 RUN/ON3 TIME/ON5 RESET SKIP 10 GND 8 11 BST3 DH3 LX3 DL3 BST5 DH5 12V AT 120mA 2.2F D1 5V OUTPUT * MAX1902 LX5 DL5 PGND CSH5 CSL5 FB5 SEQ REF 17 19 20 14 13 12 15 9 0.1F T2 0.1F 1:2.2 * C2 Q4 1N5819 3V ON/OFF 5V ON/OFF 2.5V REF 1F POWER-GOOD *VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED FOR THE MAX1902 ONLY (SEE THE OUTPUT OVERVOLTAGE PROTECTION AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS). Figure 10. Triple Output Application for MAX1902 28 ______________________________________________________________________________________ 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 ON/OFF INPUT 6V TO 24V C3 10 4.7F BST5 Q1 5V OUTPUT R1 0.1F L1 0.1F LX5 LX3 DH5 BST3 DH3 0.1F L2 Q4 R2 3.3V OUTPUT C2 1N5819 CSH3 CSL3 OPEN FB5 0 ON/OFF ON/OFF TIME/ON5 RUN/ON3 STEER GND REF SYNC SEQ FB3 RESET SKIP RESET OUTPUT 0 Q3 0.1F 0.1F V+ SHDN SECFB VL 4.7F * * 5V ALWAYS ON * C1 1N5819 Q2 DL5 MAX1901 DL3 MAX1904 * PGND CSH5 CSL5 OPEN 1F *VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED FOR THE MAX1901 ONLY (SEE THE OUTPUT OVERVOLTAGE PROTECTION AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS). Figure 11. Dual 6A Notebook Computer Power Supply ______________________________________________________________________________________ 29 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Selector Guide DEVICE MAX1901 MAX1902 MAX1904 AUXILLARY OUTPUT None (SECFB input) 12V Linear Regulator None (SECFB input) SECONDARY FEEDBACK Selectable (STEER pin) Feeds into the 5V SMPS Selectable (STEER pin) OVER/UNDERVOLTAGE PROTECTION Yes Yes No Pin Configurations TOP VIEW CSH3 1 CSL3 2 FB3 3 12OUT 4 VDD 5 SYNC 6 TIME/ON5 7 GND 8 REF 9 SKIP 10 RESET 11 FB5 12 CSL5 13 CSH5 14 28 RUN/ON3 27 DH3 26 LX3 25 BST3 24 DL3 CSH3 1 CSL3 2 FB3 3 STEER 4 SECFB 5 SYNC 6 TIME/ON5 7 GND 8 REF 9 SKIP 10 RESET 11 FB5 12 CSL5 13 CSH5 14 28 RUN/ON3 27 DH3 26 LX3 25 BST3 MAX1902 23 SHDN 22 V+ 21 VL 20 PGND 19 DL5 18 BST5 17 LX5 16 DH5 15 SEQ MAX1901 MAX1904 24 DL3 23 SHDN 22 V+ 21 VL 20 PGND 19 DL5 18 BST5 17 LX5 16 DH5 15 SEQ RUN/ON3 CSH3 CSL3 N.C. FB3 DH3 LX3 32 31 30 29 28 27 26 25 N.C. SSOP SSOP STEER SECFB SYNC TIME/ON5 GND N.C. REF SKIP 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 24 23 22 21 BST3 DL3 SHDN V+ VL PGND DL5 BST5 MAX1904 20 19 18 17 RESET 9 FB5 CSL5 DH5 CSH5 32 THIN QFN 5mm x 5mm 30 ______________________________________________________________________________________ N.C. SEQ LX5 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) SSOP.EPS MAX1901/MAX1902/MAX1904 2 1 INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015 MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L 0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0 0.212 0.311 0.037 8 5.20 7.65 0.63 0 5.38 7.90 0.95 8 0.0256 BSC 0.65 BSC N A C e D B A1 L NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. REV. 21-0056 C 1 1 ______________________________________________________________________________________ 31 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers MAX1901/MAX1902/MAX1904 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 0.15 C A D2 C L D b D2/2 0.10 M C A B PIN # 1 I.D. D/2 0.15 C B k PIN # 1 I.D. 0.35x45 E/2 E2/2 E (NE-1) X e C L E2 k L DETAIL A e (ND-1) X e C L C L L e 0.10 C A 0.08 C e L C A1 A3 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm DOCUMENT CONTROL NO. REV. APPROVAL 21-0140 C 1 2 32 ______________________________________________________________________________________ QFN THIN 5x5x0.8 .EPS 500kHz Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX1901/MAX1902/MAX1904 COMMON DIMENSIONS EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm DOCUMENT CONTROL NO. REV. APPROVAL 21-0140 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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